A speed-oriented, fully-automatic layout program for random logic VLSI devices

This paper describes a low cost, quick turnaround capability for generating high performance, random logic LSI and VLSI devices using the Standard Cell approach. This standard cell approach, described below, utilizes a fully automatic layout capability that automatically maximizes the speed of logic paths identified by the user as critical. In spite of the sophistication and size of the automatic layout program, the system can be run on Midicomputer based systems as well as time shared Main Frame Central systems. During the last 10 years over 1000 custom LSI devices have been fabricated using these techniques. During this period the basic algorithms used in these automatic layout programs passed through a series of changes due, in no small part, to the needs and demands of a rapidly changing LSI technology. Three fundamental changes occurred during this period.